High-mobility semiconductors, such as germanium, silicon germanium and compound semiconductors (e.g., III-V compound semiconductors) may be desirable to use in the fabrication of semiconductor devices because of their relatively high electron and/or hole mobility. Devices formed with high-mobility semiconductor materials may theoretically exhibit better performance, faster speeds, reduced power consumption, and have higher breakdown fields compared to similar devices formed with a lower-mobility semiconductor, such as silicon.
High-mobility semiconductor material may be used, for example, to fabricate metal oxide field effect (MOSFET) devices. A typical MOSFET device includes a source region, a drain region, and a channel region, each formed of a semiconductor material. The MOSFET also includes a dielectric material (gate dielectric) and a conductive material (e.g., metal) overlying the channel region. The dielectric material and the conductive material may be formed by depositing the respective materials using vacuum or gas-phase deposition techniques, such as, chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or the like.
Unfortunately, the interface between the channel region of the device, formed of high-mobility semiconductor materials such as germanium, silicon germanium or III-V semiconductor materials, and the gate dielectric (e.g., high dielectric constant (k) materials) typically includes a large interface trap density (Dit). The high Dit values are thought to result from vacancies and dangling bonds at the surface of the high-mobility semiconductor material, and the high Dit values deleteriously affect the performance of devices formed with the high-mobility materials and provide a technical challenge to the development of complementary metal oxide semiconductor (CMOS) devices using such high-mobility semiconductor materials.
Various approaches to passivate a high-mobility semiconductor surface prior to dielectric deposition, in order to achieve reduced interface trap densities, have been tried. For example, III-V semiconductor materials passivated with sulfur by immersing the material in wet chemical (NH4)2S solutions have shown improved interface properties, resulting in improved device performance. However, the immersion based passivation process is difficult to integrate into a vacuum or gas-phase deposition system used for subsequent dielectric material deposition. Consequently, there is an undesired air exposure time following sulfur passivation using wet chemical solution techniques and prior to the subsequent deposition of the dielectric material. This air exposure can severely affect the device performance, since the passivation layer cannot fully prevent oxide regrowth during this exposure, and oxide growth on germanium, silicon germanium and III-V semiconductor surfaces generally increases Dit. Additionally, performing solution-based passivation at elevated temperatures (e.g., >100° C.) is problematic.
In additional processes, oxide regrowth due to air exposure post etching of the high-mobility semiconductor surface may be reduced by a passivation process. For example, the passivation process may include exposing the etched semiconductor surface to a metal containing precursor, such as trimethylaluminum (TMA). However, such passivation processes may be non-ideal as the processes may in general leave a defected semiconductor surface due to incomplete passivation of the semiconductor surface.
Accordingly, improved methods and systems for passivating a surface of a semiconductor material, and particularly a high-mobility semiconductor material, and devices formed using the methods and systems are desired.